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				 David 
				Scogin 
				   
				
				Employment History: 
				  
				
				8/95-3/2004, Engineering Technician at Intel Co. 
				
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				While assistant to the Head of the Intel Training 
				Department at the Intel Santa Clara Site, I helped streamline 
				the training program by working with engineers and technicians 
				to rewrite all departments tool specification books for an 
				easier and more efficient read resulting quicker certification 
				times.   
				
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				While assistant, I help manage and organize over 
				320 Intel employees training development road map which resulted 
				in the peers successful career path at Intel. I also created 
				class schedules and sent out updates and reminders to many 
				different Intel sites.  
				
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				Instructor for Intel University classes to teach 
				peers on subjects such as general safety and output improvement 
				which resulted in many awards and recognitions for myself. 
				
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				Created a Safety Carnival for all departments to 
				teach a fun way to learn about safety. 
				
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				Leader and driver of the Suggestion Team which 
				implemented our team ideas as well as suggestions of those peers 
				outside the team which aligned with the Intel Missions and 
				Values statement. We completed a variety of project ideas from 
				training peers how to write YLR’s (yield learning reports) on 
				quality mishaps to redesigning and modifying some tool sets to 
				run more efficiently.   
				
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				Planning and Goaling Coordinator for Planar and 
				responsible for safety, quality, and output of peers.  
				
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				Awarded peers for positive behavior in safety and 
				quality.  
				
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				Runner-up for an Oregon wide safety logo contest. 
				
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				Hazmat Representative for Planar area and member 
				of the ERT (Emergency Response Team). 
				
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				Leader and driver of a Quality Team, which was 
				created by myself because of the continued  
				
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				constraint problems with certain fab(factory) 
				areas. Here I drove several quality-related fixes to the fab 
				(plant) floor which raised wafer line and die (microprocessor) 
				yields increasing Intel’s bottom line. Other Intel sites also 
				adopted many of our quality related fixes which exponentially 
				help raise Intel’s bottom line.  
				
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				Quality Assurance Engineering Technician in 
				Lithography.  
				
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				Always quick to volunteer and recognized from 
				fellow engineers and peers for that.  
				  
				
				5/93-3/95, F/A-18 Aviation Ordnanceman at U.S. Marine Corps
				 
				
				·        
				Performed PM’s, electrical and mechanical 
				maintenance on all related ordnance equipment such as bomb racks 
				on the F/A-18 Aircraft. Trained other Marines into this field. 
				Supervised subordinates. Performed in a teamwork environment 
				daily. 
				  
				
				Education: 
				  
				TEFL Certificate, certified at Talk and 
				Text Academy, GPA: n/a   
				Incomplete Bachelor of Science in Business 
				Marketing, University of Phoenix, GPA: 3.95  
				English, math, Mission College, GPA: 3.2 
				Semiconductor Industry, Intel University, 
				GPA: n/a 
				Certification in F/A-18 Aviation Ordnance, 
				NAS Memphis GPA: 3.4 
				Degree in Mechanics, Marshall High School, 
				GPA: 3.2  |